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| author | Mogball <jeffniu22@gmail.com> | 2022-03-04 20:23:24 +0000 |
|---|---|---|
| committer | Mogball <jeffniu22@gmail.com> | 2022-03-04 20:33:14 +0000 |
| commit | e7c7b16a849fb40169a708d27cb59747139ed8c7 (patch) | |
| tree | 60246b832a43146393233de3f33b939cca734f2a /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | e22e2774d93379d6bad41ae20194b076fdb44915 (diff) | |
| download | llvm-e7c7b16a849fb40169a708d27cb59747139ed8c7.zip llvm-e7c7b16a849fb40169a708d27cb59747139ed8c7.tar.gz llvm-e7c7b16a849fb40169a708d27cb59747139ed8c7.tar.bz2 | |
[mlir] Region/BranchOpInterface: Allow implicit type conversions along control-flow edges
RegionBranchOpInterface and BranchOpInterface are allowed to make implicit type conversions along control-flow edges. In effect, this adds an interface method, `areTypesCompatible`, to both interfaces, which should return whether the types of corresponding successor operands and block arguments are compatible. Users of the interfaces, here on forth, must be aware that types may mismatch, although current users (in MLIR core), are not affected by this change. By default, type equality is used.
`async.execute` already has unequal types along control-flow edges (`!async.value<f32>` vs. `f32`), but it opted out of calling `RegionBranchOpInterface::verifyTypes` in its verifier. That method has now been removed and `RegionBranchOpInterface` will verify types along control edges by default in its verifier.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D120790
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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