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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-06-09 20:05:05 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-06-15 07:42:20 -0400 |
| commit | dae9554b2b039db403a77461fdb95239d6c06a96 (patch) | |
| tree | a2959fb80ff4dd566fb47e93ed3f90b551107f07 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 96229606f964f7b32d233ea14767529fe807c48c (diff) | |
| download | llvm-dae9554b2b039db403a77461fdb95239d6c06a96.zip llvm-dae9554b2b039db403a77461fdb95239d6c06a96.tar.gz llvm-dae9554b2b039db403a77461fdb95239d6c06a96.tar.bz2 | |
AMDGPU/GlobalISel: Workaround some load/store type selection patterns
The logic is written for what loads/stores should be selectable. There
are a set of cases that should be selectable, but due to missing MVTs
and/or selection patterns, will fail to select. I think eventually
load/store select patterns should ignore the type and only look at the
value size, but until that happens, bitcast these to equivalent i32
vectors.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions