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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-08-14 22:06:05 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-08-14 22:06:05 +0000 |
| commit | cd357872178619781f17ced87364c056d7a84c98 (patch) | |
| tree | 6620c2d059a1b3dfd268a285f72c9f956f58e43f /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 24ac55d8841d1c1782d989af6e87c4502c6bda33 (diff) | |
| download | llvm-cd357872178619781f17ced87364c056d7a84c98.zip llvm-cd357872178619781f17ced87364c056d7a84c98.tar.gz llvm-cd357872178619781f17ced87364c056d7a84c98.tar.bz2 | |
[AArch64] Fix FMLS scalar-indexed-from-2s-after-neg patterns.
We canonicalize V64 vectors to V128 through insert_subvector: the other
FMLA/FMLS/FMUL/FMULX patterns match that already, but this one doesn't,
so we'd fail to match fmls and generate fneg+fmla instead.
The vector equivalents are already tested and functional.
llvm-svn: 245107
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions