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author | Fraser Cormack <fraser@codeplay.com> | 2021-06-09 15:17:21 +0100 |
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committer | Fraser Cormack <fraser@codeplay.com> | 2021-06-14 18:12:18 +0100 |
commit | c75e454cb93206833f8cedde1ed5d12ef161e357 (patch) | |
tree | f53117975d97f2d90a50273f51733da95b3e65b0 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
parent | c58cf692f4197bf1f8ea7e0efb95c1afd2d6d81f (diff) | |
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[RISCV] Transform unaligned RVV vector loads/stores to aligned ones
This patch adds support for loading and storing unaligned vectors via an
equivalently-sized i8 vector type, which has support in the RVV
specification for byte-aligned access.
This offers a more optimal path for handling of unaligned fixed-length
vector accesses, which are currently scalarized. It also prevents
crashing when `LegalizeDAG` sees an unaligned scalable-vector load/store
operation.
Future work could be to investigate loading/storing via the largest
vector element type for the given alignment, in case that would be more
optimal on hardware. For instance, a 4-byte-aligned nxv2i64 vector load
could loaded as nxv4i32 instead of as nxv16i8.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D104032
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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