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| author | S. VenkataKeerthy <31350914+svkeerthy@users.noreply.github.com> | 2025-10-22 10:58:38 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-22 10:58:38 -0700 |
| commit | c70d0812ba17953b3e405eb2b01dd892b94585f1 (patch) | |
| tree | 8c64562817513cefd583a3c06862fcba12b4efc3 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 6c8ad30a82a7ed240cbc3abc07c6759905fecd5b (diff) | |
| download | llvm-c70d0812ba17953b3e405eb2b01dd892b94585f1.zip llvm-c70d0812ba17953b3e405eb2b01dd892b94585f1.tar.gz llvm-c70d0812ba17953b3e405eb2b01dd892b94585f1.tar.bz2 | |
[MIR2Vec] Handle Operands (#163281)
Handling opcodes in embedding computation.
- Revamped MIR Vocabulary with four sections - `Opcodes`, `Common Operands`, `Physical Registers`, and `Virtual Registers`
- Operands broadly fall into 3 categories -- the generic MO types that are common across architectures, physical and virtual register classes. We handle these categories separately in MIR2Vec. (Though we have same classes for both physical and virtual registers, their embeddings vary).
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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