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| author | Craig Topper <craig.topper@intel.com> | 2017-11-04 06:44:47 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-04 06:44:47 +0000 |
| commit | a96d62b360b873046035ba439053cd4de2ff1470 (patch) | |
| tree | 511ab85f17361886809e25757046c6dcf193c208 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 965429ee522b01b94a9a9d01b46ac10e804029f1 (diff) | |
| download | llvm-a96d62b360b873046035ba439053cd4de2ff1470.zip llvm-a96d62b360b873046035ba439053cd4de2ff1470.tar.gz llvm-a96d62b360b873046035ba439053cd4de2ff1470.tar.bz2 | |
[X86] Teach shuffle lowering to use 256-bit SHUF128 when possible.
This allows masked operations to be used and allows the register allocator to use YMM16-31 if necessary.
As a follow up I'll look into teaching EVEX->VEX how to turn this back into PERM2X128 if any of the additional features don't work out.
llvm-svn: 317403
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions