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authorDavid Sherwood <david.sherwood@arm.com>2020-06-25 08:19:49 +0100
committerDavid Sherwood <david.sherwood@arm.com>2020-07-07 09:23:04 +0100
commit79d34a5a1bce39d8153be3665456e9cb0cc8601b (patch)
treec17c42e19da43ebec076cc3bbfa933be72ee1a26 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parentc061e56e880a20488e0f7e6cf9975aa24b83067c (diff)
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[SVE][CodeGen] Fix bug when falling back to DAG ISel
In an earlier commit 584d0d5c1749c13625a5d322178ccb4121eea610 I added functionality to allow AArch64 CodeGen support for falling back to DAG ISel when Global ISel encounters scalable vector types. However, it seems that we were not falling back early enough as llvm::getLLTForType was still being invoked for scalable vector types. I've added a new fallback function to the call lowering class in order to catch this problem early enough, rather than wait for lowerFormalArguments to reject scalable vector types. Differential Revision: https://reviews.llvm.org/D82524
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