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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-05-12 14:18:53 -0700 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-05-12 16:05:12 -0700 |
| commit | 71ed66d97fd624313bef693fa9da54fa66bdcd09 (patch) | |
| tree | a1b1d2be34e2cd7525daf4645b5ee099ed5e881d /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | ab22f71dd75895fbde1cd1a515b2164227d5dfd2 (diff) | |
| download | llvm-71ed66d97fd624313bef693fa9da54fa66bdcd09.zip llvm-71ed66d97fd624313bef693fa9da54fa66bdcd09.tar.gz llvm-71ed66d97fd624313bef693fa9da54fa66bdcd09.tar.bz2 | |
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
We can produce such vectors in the Promote Alloca pass,
but we are unable to use movrel to operate it and lower
via scratch. Making it legal makes SI_INDIRECT patterns
work.
There is more work to do in subsequent changes:
1. We initialize m0 twice to access each dword. It shall
be possible to only do it once and increment base register
number instead.
2. We also need v16i64/v16f64 but these first need to be
added to tablegen.
Differential Revision: https://reviews.llvm.org/D79808
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions