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| author | Caroline Concatto <caroline.concatto@arm.com> | 2022-11-02 09:35:43 +0000 |
|---|---|---|
| committer | Caroline Concatto <caroline.concatto@arm.com> | 2022-11-04 09:11:07 +0000 |
| commit | 529a932e3fb7db5da29134e152281e7615baf36e (patch) | |
| tree | a1d3da53a832b4cd3bfb4ad1129bd821832f9754 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 50621169ae1efb4998cc64dcd9d5bab6941486de (diff) | |
| download | llvm-529a932e3fb7db5da29134e152281e7615baf36e.zip llvm-529a932e3fb7db5da29134e152281e7615baf36e.tar.gz llvm-529a932e3fb7db5da29134e152281e7615baf36e.tar.bz2 | |
[AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers
This patch adds the assembly/disassembly for the following instructions:
SUNPK: Unpack and sign-extend multi-vector elements.
UUNPK: Unpack and zero-extend multi-vector elements.
ZIP (four registers): Interleave elements from four vectors.
ZIP (two registers): Interleave elements from two vectors.
FRINTA: Multi-vector floating-point round to integral value, to nearest with ties away from zero.
FRINTM: Multi-vector floating-point round to integral value, toward minus Infinity.
FRINTN: Multi-vector floating-point round to integral value, to nearest with ties to even.
FRINTP: Multi-vector floating-point round to integral value, toward plus Infinity.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136091
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions