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| author | Craig Topper <craig.topper@sifive.com> | 2022-07-09 11:40:53 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-07-09 11:53:44 -0700 |
| commit | 40866b74bd422ae72ad53270d04568249ed53d69 (patch) | |
| tree | 9535d9d77cbce08e8270673645e29584994dc9b9 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 0660f3c5a0a083cef78f39b3105a9a8e27cf5095 (diff) | |
| download | llvm-40866b74bd422ae72ad53270d04568249ed53d69.zip llvm-40866b74bd422ae72ad53270d04568249ed53d69.tar.gz llvm-40866b74bd422ae72ad53270d04568249ed53d69.tar.bz2 | |
[DAGCombiner][X86] Fold sra (sub AddC, (shl X, N1C)), N1C --> sext (sub AddC1',(trunc X to (width - N1C)))
We already handled this case for add with a constant RHS. A
similar pattern can occur for sub with a constant left hand side.
Test cases use add and a mul representing (neg (shl X, C)) because
that's what I saw in the wild. The mul will be decomposed and then
the new transform can kick in.
Tests have not been committed, but this patch shows the changes.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D128769
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions