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| author | Craig Topper <craig.topper@sifive.com> | 2021-12-14 09:54:24 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-12-14 10:17:57 -0800 |
| commit | 3f1c403a2b0a60198aee1c69ee2be7c0aa3a70e8 (patch) | |
| tree | a5ac66f1ecb070578406f647ec8bf68b48e23ba8 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 1042de90589c74c6998c127d1ee1b33ff3efb8cc (diff) | |
| download | llvm-3f1c403a2b0a60198aee1c69ee2be7c0aa3a70e8.zip llvm-3f1c403a2b0a60198aee1c69ee2be7c0aa3a70e8.tar.gz llvm-3f1c403a2b0a60198aee1c69ee2be7c0aa3a70e8.tar.bz2 | |
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
In order to support constrained FP intrinsics we need to model FRM
dependency. Whether or not a instruction uses FRM is based on a 3
bit field in the instruction. Because of this we can't add
'Uses = [FRM]' to the tablegen descriptions.
This patch examines the immediate after isel and adds an implicit
use of FRM. This idea came from Roger Ferrer Ibanez.
Other ideas:
We could be overly conservative and just pretend all instructions with
frm field read the FRM register. Or we could have pseudoinstructions
for CodeGen with rounding mode.
Reviewed By: asb, frasercrmck, arcbbb
Differential Revision: https://reviews.llvm.org/D115555
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions