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| author | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2016-12-21 08:31:45 +0000 |
|---|---|---|
| committer | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2016-12-21 08:31:45 +0000 |
| commit | 3b95157090110e8e9f41903ec2d04db372470b03 (patch) | |
| tree | 42dcb7d63c47b7e060492acf582e3d0ec04ad0d4 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | dcf5b72e20e331ee90450029033bb993dbf69cbd (diff) | |
| download | llvm-3b95157090110e8e9f41903ec2d04db372470b03.zip llvm-3b95157090110e8e9f41903ec2d04db372470b03.tar.gz llvm-3b95157090110e8e9f41903ec2d04db372470b03.tar.bz2 | |
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible.
vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use.
The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above.
The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it.
This aubmit also includes additional lit tests to cover better HVAs corner cases.
Differential Revision: https://reviews.llvm.org/D27392
llvm-svn: 290240
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions