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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-10-08 11:19:54 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-08 11:19:54 +0900 |
| commit | 1a5494ca4a7d2e6884e17c064e5215b34fbe4b40 (patch) | |
| tree | 216fc93f04d63adaca92df9c249f0df663f9f769 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 760a1142feee734d044ab546914407f6b8d96062 (diff) | |
| download | llvm-1a5494ca4a7d2e6884e17c064e5215b34fbe4b40.zip llvm-1a5494ca4a7d2e6884e17c064e5215b34fbe4b40.tar.gz llvm-1a5494ca4a7d2e6884e17c064e5215b34fbe4b40.tar.bz2 | |
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
This removes special case processing in TargetInstrInfo::getRegClass to
fixup register operands which depending on the subtarget support AGPRs,
or require even aligned registers.
This regresses assembler diagnostics, which currently work by hackily
accepting invalid cases and then post-rejecting a validly parsed
instruction.
On the plus side this now emits a comment when disassembling unaligned
registers for targets with the alignment requirement.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions