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| author | Craig Topper <craig.topper@sifive.com> | 2021-07-17 00:24:48 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-07-17 00:52:07 -0700 |
| commit | 173332d175614561770469d237f8c5ba6378a0e7 (patch) | |
| tree | efdf8b101ec65b18f9f0ec5b4cdbb9a4e49462f4 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 1f1369e4769945e3d975bc4d7c7a9db30ed47b04 (diff) | |
| download | llvm-173332d175614561770469d237f8c5ba6378a0e7.zip llvm-173332d175614561770469d237f8c5ba6378a0e7.tar.gz llvm-173332d175614561770469d237f8c5ba6378a0e7.tar.bz2 | |
[RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.
We assume VLENB is a multiple of 8 and previously relied on shift
pairs being optimized to an AND+SHL/SHR and computeKnownBits
removing the AND. This doesn't happen if (vlenb >> 3) gets CSEd
to have multiple uses. This patch manually emits the best shift
to workaround this.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions