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author | Simon Tatham <simon.tatham@arm.com> | 2020-02-17 17:06:05 +0000 |
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committer | Simon Tatham <simon.tatham@arm.com> | 2020-02-18 09:34:50 +0000 |
commit | 5e97940cd27961a0b872ff551fc98135507288b3 (patch) | |
tree | ef16a0f5b3cc3226dbf0874143ce6d77bdfd0961 /llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp | |
parent | 9dcc1667abfc49bf6d44688a02e12cd96244ea72 (diff) | |
download | llvm-5e97940cd27961a0b872ff551fc98135507288b3.zip llvm-5e97940cd27961a0b872ff551fc98135507288b3.tar.gz llvm-5e97940cd27961a0b872ff551fc98135507288b3.tar.bz2 |
[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp')
0 files changed, 0 insertions, 0 deletions