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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2021-11-01 14:22:10 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-02-07 10:02:03 -0500 |
| commit | 31973062ec2290004f67eeb0aa6f468d1f2f1a86 (patch) | |
| tree | d0bd174783f8cbcf216b7dacf2f866370635249c /llvm/lib/Bitcode/Reader/BitReader.cpp | |
| parent | be826cf4f71a7f9b7e9160b84c6c7e99e19a642f (diff) | |
| download | llvm-31973062ec2290004f67eeb0aa6f468d1f2f1a86.zip llvm-31973062ec2290004f67eeb0aa6f468d1f2f1a86.tar.gz llvm-31973062ec2290004f67eeb0aa6f468d1f2f1a86.tar.bz2 | |
AMDGPU: Fix clobbering SCC when expanding large offset spill pseudos
If we had a large offset which required materializing in a register,
we would emit an s_add_i32, clobbering SCC. Start checking if SCC is
live, and instead use a VGPR offset. For MUBUF, we switch to using
offen. We would do this anyway in a normal load/store with a frame
index, but not for spills.
The same problem still exists in other contexts where we expand frame
indices.
The nasty edge case is when SGPRs are spilled to memory at a large
frame offset where SCC is also clobbered. This requires a second
scavenging index, and also required several patches in the scavenger
to correctly handle multiple recursive scavenge indexes.
An even nastier edge case we still don't support is if we don't have
any free SGPRs. If SCC is live and we don't have any free SGPRs to
save exec, we have no way of flipping exec back and forth without also
clobbering SCC.
Fixes: SWDEV-309419
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitReader.cpp')
0 files changed, 0 insertions, 0 deletions