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| author | Craig Topper <craig.topper@sifive.com> | 2023-11-24 08:49:19 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-24 08:49:19 -0800 |
| commit | d9962c400f970d17396e84c1a55cdbea29a7c893 (patch) | |
| tree | 148b09a26214ed5534441c041ec7136372bfff34 /llvm/lib/AsmParser/LLLexer.cpp | |
| parent | 5d501b1091ce3632b885c60a8fc9f74ed9c95ae3 (diff) | |
| download | llvm-d9962c400f970d17396e84c1a55cdbea29a7c893.zip llvm-d9962c400f970d17396e84c1a55cdbea29a7c893.tar.gz llvm-d9962c400f970d17396e84c1a55cdbea29a7c893.tar.bz2 | |
[IR] Add disjoint flag for Or instructions. (#72583)
This flag indicates that every bit is known to be zero in at least one
of the inputs. This allows the Or to be treated as an Add since there is
no possibility of a carry from any bit.
If the flag is present and this property does not hold, the result is
poison.
This makes it easier to reverse the InstCombine transform that turns Add
into Or.
This is inspired by a comment here
https://github.com/llvm/llvm-project/pull/71955#discussion_r1391614578
Discourse thread
https://discourse.llvm.org/t/rfc-add-or-disjoint-flag/75036
Diffstat (limited to 'llvm/lib/AsmParser/LLLexer.cpp')
| -rw-r--r-- | llvm/lib/AsmParser/LLLexer.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index fb11104..09a205c 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -564,6 +564,7 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(nuw); KEYWORD(nsw); KEYWORD(exact); + KEYWORD(disjoint); KEYWORD(inbounds); KEYWORD(nneg); KEYWORD(inrange); |