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| author | Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> | 2015-10-12 09:57:00 +0000 |
|---|---|---|
| committer | Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> | 2015-10-12 09:57:00 +0000 |
| commit | b352a1c88fb5dd3207de4700100743329fcb7626 (patch) | |
| tree | dd1f8df87223673c4e7c0db518dd7cbc4c816f18 /llvm/lib/Analysis/VectorUtils.cpp | |
| parent | c3741ec8d364bb2490cf4abc0d3128cbad51f169 (diff) | |
| download | llvm-b352a1c88fb5dd3207de4700100743329fcb7626.zip llvm-b352a1c88fb5dd3207de4700100743329fcb7626.tar.gz llvm-b352a1c88fb5dd3207de4700100743329fcb7626.tar.bz2 | |
X86: Change FTAG register size in FXSAVE structure
Summary:
- Changed from 16 bits to 8 bits for Intel Architecture
-- FXSAVE structure now conforms with the layout of FXSAVE
area specified by IA Architecture Software Developer Manual
- Modified Linux and FreeBSD specific files to support this change
-- MacOSX already uses 8 bits for ftag register
- Modified TestRegisters.py and a.cpp:
-- Change allows 8 bit comparison of ftag values
-- Change resolves Bug 24733:
Removed XFAIL for Clang as the test works and passes for
Clang compiler as well
-- Change provides a Generic/Better way of testing Bug 24457
and Bug 25050 by using 'int3' inline assembly in inferior
Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>
Reviewers: ovyalov, jingham, clayborg
Subscribers: tfiala, emaste
Differential Revision: http://reviews.llvm.org/D13587
llvm-svn: 250022
Diffstat (limited to 'llvm/lib/Analysis/VectorUtils.cpp')
0 files changed, 0 insertions, 0 deletions