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| author | Muhammad Omair Javaid <omair.javaid@linaro.org> | 2025-08-01 01:07:31 +0500 |
|---|---|---|
| committer | Muhammad Omair Javaid <omair.javaid@linaro.org> | 2025-08-01 01:24:52 +0500 |
| commit | 176d54aa33104b6de2979ffb3dc52f3a187bed17 (patch) | |
| tree | 06dffc7fa1375283b532b93b0a19f9892082de8a /llvm/lib/Analysis/VectorUtils.cpp | |
| parent | bf7afe1dc9c36011457c57b87cbe48e89f105ce4 (diff) | |
| download | llvm-176d54aa33104b6de2979ffb3dc52f3a187bed17.zip llvm-176d54aa33104b6de2979ffb3dc52f3a187bed17.tar.gz llvm-176d54aa33104b6de2979ffb3dc52f3a187bed17.tar.bz2 | |
Revert "[VectorUtils] Trivially vectorize ldexp, [l]lround (#145545)"
This reverts commit 13366759c3b9db9366659d870cc73c938422b020.
This broke various LLVM testsuite buildbots for AArch64 SVE, but the
problem got masked because relevant buildbots were already failing
due to other breakage.
It has broken llvm-test-suite test:
gfortran-regression-compile-regression__vect__pr106253_f.test
https://lab.llvm.org/buildbot/#/builders/4/builds/8164
https://lab.llvm.org/buildbot/#/builders/17/builds/9858
https://lab.llvm.org/buildbot/#/builders/41/builds/8067
https://lab.llvm.org/buildbot/#/builders/143/builds/9607
Diffstat (limited to 'llvm/lib/Analysis/VectorUtils.cpp')
| -rw-r--r-- | llvm/lib/Analysis/VectorUtils.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index 425ea31..b3b4c37 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -81,7 +81,6 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) { case Intrinsic::exp: case Intrinsic::exp10: case Intrinsic::exp2: - case Intrinsic::ldexp: case Intrinsic::log: case Intrinsic::log10: case Intrinsic::log2: @@ -109,8 +108,6 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) { case Intrinsic::canonicalize: case Intrinsic::fptosi_sat: case Intrinsic::fptoui_sat: - case Intrinsic::lround: - case Intrinsic::llround: case Intrinsic::lrint: case Intrinsic::llrint: case Intrinsic::ucmp: @@ -192,8 +189,6 @@ bool llvm::isVectorIntrinsicWithOverloadTypeAtArg( switch (ID) { case Intrinsic::fptosi_sat: case Intrinsic::fptoui_sat: - case Intrinsic::lround: - case Intrinsic::llround: case Intrinsic::lrint: case Intrinsic::llrint: case Intrinsic::vp_lrint: @@ -208,7 +203,6 @@ bool llvm::isVectorIntrinsicWithOverloadTypeAtArg( case Intrinsic::vp_is_fpclass: return OpdIdx == 0; case Intrinsic::powi: - case Intrinsic::ldexp: return OpdIdx == -1 || OpdIdx == 1; default: return OpdIdx == -1; |