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authorCraig Topper <craig.topper@intel.com>2019-01-11 05:44:56 +0000
committerCraig Topper <craig.topper@intel.com>2019-01-11 05:44:56 +0000
commitb97885cc2eb06a29141b6ea67413f8ff17afcc10 (patch)
tree4efe991c68744b4db80a1bd1e47ee6359bfe9361 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
parentd458ceda24fde3bc0f2f910b80e3bd9f990af2fa (diff)
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[X86] Change vXi1 extract_vector_elt lowering to be legal if the index is 0. Add DAG combine to turn scalar_to_vector+extract_vector_elt into extract_subvector.
We were lowering the last step extract_vector_elt to a bitcast+truncate. Change it to use an extract_vector_elt of index 0 instead. Add isel patterns to do the equivalent of what the bitcast would have done. Plus an isel pattern for an any_extend+extract to prevent some regressions. Finally add a DAG combine to turn v1i1 scalar_to_vector+extract_vector_elt of 0 into an extract_subvector. This fixes some of the regressions from D350800. llvm-svn: 350918
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