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| author | Shiva Chen <shiva0217@gmail.com> | 2018-02-22 15:02:28 +0000 |
|---|---|---|
| committer | Shiva Chen <shiva0217@gmail.com> | 2018-02-22 15:02:28 +0000 |
| commit | 7c17242b9215d6ac1eacf4a7ed397c672a2b07e9 (patch) | |
| tree | 3255323376aff1207390cb6326948a230def435d /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | 6c1e6bbe0c609489ef49f9d64f1370a43e05c19c (diff) | |
| download | llvm-7c17242b9215d6ac1eacf4a7ed397c672a2b07e9.zip llvm-7c17242b9215d6ac1eacf4a7ed397c672a2b07e9.tar.gz llvm-7c17242b9215d6ac1eacf4a7ed397c672a2b07e9.tar.bz2 | |
[RISCV] Implement c.lui immediate operand constraint
Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff].
The RISC-V ISA describes the constraint as [1, 63], with that value
being loaded in to bits 17-12 of the destination register and sign extended
from bit 17. Therefore, this 6-bit immediate can represent values in the
ranges [1, 31] and [0xfffe0, 0xfffff].
Differential Revision: https://reviews.llvm.org/D42834
llvm-svn: 325792
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions