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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2025-10-01 15:38:15 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-01 14:38:15 +0000 |
| commit | 50c8e5d730ac55454ef5c1f58fbc9096e946240c (patch) | |
| tree | 858403b35058107739b571c19d859de9ce677f95 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | 8f77621574176387f906b8ceef9e1abb90bf22f6 (diff) | |
| download | llvm-50c8e5d730ac55454ef5c1f58fbc9096e946240c.zip llvm-50c8e5d730ac55454ef5c1f58fbc9096e946240c.tar.gz llvm-50c8e5d730ac55454ef5c1f58fbc9096e946240c.tar.bz2 | |
[X86] SimplifyDemandedBitsForTargetNode - generalize X86ISD::VSRAI handling when only demanding 'known signbits' (#161523)
If we only demand bits that already match the signbit then we don't need to shift.
Generalizes an existing pattern that just handled signbit-only demanded bits to match what we do for ISD::SRA.
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions