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| author | David Sherwood <david.sherwood@arm.com> | 2023-07-24 12:34:42 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2023-07-25 08:55:45 +0000 |
| commit | 4cf11d8a65dfded59761ec52804a86277b9c0036 (patch) | |
| tree | 00f0dc0a8890ed93f3d3bb525b097b20aa530129 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | 86da763ab6ed19c58349d3f6f62d4bb52becab2c (diff) | |
| download | llvm-4cf11d8a65dfded59761ec52804a86277b9c0036.zip llvm-4cf11d8a65dfded59761ec52804a86277b9c0036.tar.gz llvm-4cf11d8a65dfded59761ec52804a86277b9c0036.tar.bz2 | |
[Clang][SVE] Permit specific predicate-as-counter registers in inline assembly
This patch adds the predicate-as-counter registers pn0-pn15 to the
list of supported registers used when writing inline assembly.
Tests added to
clang/test/CodeGen/aarch64-sve-inline-asm.c
Differential Revision: https://reviews.llvm.org/D156115
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions