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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-11-10 10:31:40 +0900 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2023-12-06 23:07:22 +0700 |
| commit | 1f283a60a4bb896fa2d37ce00a3018924be82b9f (patch) | |
| tree | 6eaa679cb222ec4d11efd63a46e059e260268ba0 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | c7b3ae5ab9c8ffc19db00bd6e995d225ac1013e9 (diff) | |
| download | llvm-1f283a60a4bb896fa2d37ce00a3018924be82b9f.zip llvm-1f283a60a4bb896fa2d37ce00a3018924be82b9f.tar.gz llvm-1f283a60a4bb896fa2d37ce00a3018924be82b9f.tar.bz2 | |
Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"
This reverts commit 9e50c6e6b5741895f58f3e530004052844b6af9f. A few assertion and verifier
errors have been fixed in the coalescer and allocator, so hopefully this sticks this time.
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions