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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-22 14:36:58 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-22 14:36:58 +0000 |
| commit | 13de555737e07b29d126ed72d8450f88bd38f66c (patch) | |
| tree | 515d1f11102597b3fc6e503635998d14c847c490 /llvm/lib/Analysis/MemoryBuiltins.cpp | |
| parent | 8a60e5db701ed04926e120142dbb7bdb0528010a (diff) | |
| download | llvm-13de555737e07b29d126ed72d8450f88bd38f66c.zip llvm-13de555737e07b29d126ed72d8450f88bd38f66c.tar.gz llvm-13de555737e07b29d126ed72d8450f88bd38f66c.tar.bz2 | |
[FastISel] Permit instructions to be skipped for FastISel generation.
Some ISA's such as microMIPS32(R6) have instructions which are near identical
for code generation purposes, e.g. xor and xor16. These instructions take the
same value types for operands and return values, have the same
instruction predicates and map to the same ISD opcode. (These instructions do
differ by register classes.)
In such cases, the FastISel generator rejects the instruction definition.
This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables
applying it to an instruction definition.
Reviewers: mcrosier
Differential Revision: https://reviews.llvm.org/D46953
llvm-svn: 332983
Diffstat (limited to 'llvm/lib/Analysis/MemoryBuiltins.cpp')
0 files changed, 0 insertions, 0 deletions