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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-03-12 20:16:40 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-03-12 20:16:57 +0000 |
| commit | e91feeed21ee16abdb73f6e8cd471a253136e2cf (patch) | |
| tree | e123069ca06231521cbbc8648d00eaf2d3a0c855 /llvm/lib/Analysis/LoopAnalysisManager.cpp | |
| parent | 9975dc38bf734b4d86eab61269080ca231379d23 (diff) | |
| download | llvm-e91feeed21ee16abdb73f6e8cd471a253136e2cf.zip llvm-e91feeed21ee16abdb73f6e8cd471a253136e2cf.tar.gz llvm-e91feeed21ee16abdb73f6e8cd471a253136e2cf.tar.bz2 | |
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions.
This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.
Differential Revision: https://reviews.llvm.org/D76070
Diffstat (limited to 'llvm/lib/Analysis/LoopAnalysisManager.cpp')
0 files changed, 0 insertions, 0 deletions