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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-04-20 11:37:53 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-06-01 09:15:41 -0400 |
| commit | a0dcbe45bd8387da51f94e4d171c3ecc3d266e64 (patch) | |
| tree | 85370b39f3ffaa80150446372a7a86f9c14d8451 /llvm/lib/Analysis/LoopAccessAnalysis.cpp | |
| parent | 2011052150e1a2fb8586b030126f8bec338f4cc5 (diff) | |
| download | llvm-a0dcbe45bd8387da51f94e4d171c3ecc3d266e64.zip llvm-a0dcbe45bd8387da51f94e4d171c3ecc3d266e64.tar.gz llvm-a0dcbe45bd8387da51f94e4d171c3ecc3d266e64.tar.bz2 | |
llvm-reduce: Add reduction pass to remove regalloc hints
I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.
Diffstat (limited to 'llvm/lib/Analysis/LoopAccessAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions