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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-04-20 16:45:25 -0700 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-04-28 13:34:24 -0700 |
| commit | 1baaa080e0481fa2a7cfafc7303c264d0a305c58 (patch) | |
| tree | f19a3882868bf5f2a715cf76d58d0fd6c024d04f /llvm/lib/Analysis/LoopAccessAnalysis.cpp | |
| parent | 8a7cf11f92e1fbc35dc754b4113e6697fa425607 (diff) | |
| download | llvm-1baaa080e0481fa2a7cfafc7303c264d0a305c58.zip llvm-1baaa080e0481fa2a7cfafc7303c264d0a305c58.tar.gz llvm-1baaa080e0481fa2a7cfafc7303c264d0a305c58.tar.bz2 | |
[AMDGPU] Define special SGPR subregs
These are used in SReg_32 and when we start to use SGPR_LO16
there will be compaints that not all registers in RC support
all subreg indexes. For now it is NFC.
Unused regunits are reserved so that verifier does not complain
about missing phys reg live-ins.
Differential Revision: https://reviews.llvm.org/D78591
Diffstat (limited to 'llvm/lib/Analysis/LoopAccessAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions