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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2014-04-26 01:03:22 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2014-04-26 01:03:22 +0000
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parent8d039e442036436c004d7b43333efe29d4386293 (diff)
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[InstCombine][X86] Teach how to fold calls to SSE2/AVX2 packed logical shift
right intrinsics. A packed logical shift right with a shift count bigger than or equal to the element size always produces a zero vector. In all other cases, it can be safely replaced by a 'lshr' instruction. llvm-svn: 207299
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