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| author | Luo, Yuanke <yuanke.luo@intel.com> | 2022-07-12 11:00:08 +0800 |
|---|---|---|
| committer | Luo, Yuanke <yuanke.luo@intel.com> | 2022-07-26 11:56:03 +0800 |
| commit | 5fb41342105700949c81f68aefc85d9c46e9a1a6 (patch) | |
| tree | 568a9e30f77e6c77b2c249258981d59081601c6a /llvm/lib/Analysis/CodeMetrics.cpp | |
| parent | 4871dfc64e35e9cf07008c56299125694c81720a (diff) | |
| download | llvm-5fb41342105700949c81f68aefc85d9c46e9a1a6.zip llvm-5fb41342105700949c81f68aefc85d9c46e9a1a6.tar.gz llvm-5fb41342105700949c81f68aefc85d9c46e9a1a6.tar.bz2 | |
[X86][DAGISel] Don't widen shuffle element with AVX512
Currently the X86 shuffle lowering would widen the element type for
shuffle if the mask element value is adjacent. For below example
%t2 = add nsw <16 x i32> %t0, %t1
%t3 = sub nsw <16 x i32> %t0, %t1
%t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3,
<16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4,
i32 5, i32 6, i32 7, i32 8, i32 9, i32 10,
i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i32> %t4
Compiler would transform the shuffle to
%t4 = shufflevector <8 x i64> %t2, <8 x i64> %t3,
<8 x i64> <i32 8, i32 1, i32 2, i32 3, i32 4,
i32 5, i32 6, i32 7>
This may lose the oppotunity to let ISel select mask instruction when
avx512 is enabled.
This patch is to prevent the tranform when avx512 feature is enabled.
Thank Simon for the idea.
Differential Revision: https://reviews.llvm.org/D129537
Diffstat (limited to 'llvm/lib/Analysis/CodeMetrics.cpp')
0 files changed, 0 insertions, 0 deletions