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| author | Jay Foad <jay.foad@amd.com> | 2021-02-09 18:11:10 +0000 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2021-02-11 17:46:09 +0000 |
| commit | 23db2d363fd3fe851197fc314f0150976e31be5e (patch) | |
| tree | 9079d544cb22a7fbebc24f4d841d1d650f59f13e /llvm/lib/Analysis/CodeMetrics.cpp | |
| parent | 5744502a137cbc9f2732e707fde984399b241515 (diff) | |
| download | llvm-23db2d363fd3fe851197fc314f0150976e31be5e.zip llvm-23db2d363fd3fe851197fc314f0150976e31be5e.tar.gz llvm-23db2d363fd3fe851197fc314f0150976e31be5e.tar.bz2 | |
[AMDGPU] Better selection of base offset when merging DS reads/writes
When merging a pair of DS reads or writes needs to materialize the base
offset in a vgpr, choose a value that is aligned to as high a power of
two as possible. This maximises the chance that different pairs can use
the same base offset, in which case the base offset registers can be
commoned up by MachineCSE.
Differential Revision: https://reviews.llvm.org/D96421
Diffstat (limited to 'llvm/lib/Analysis/CodeMetrics.cpp')
0 files changed, 0 insertions, 0 deletions