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| author | Srinivasa Ravi <srinivasar@nvidia.com> | 2025-02-01 11:32:44 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-01 11:32:44 +0530 |
| commit | 83cad6805d144d941bdda99d71a6df2cf113a76d (patch) | |
| tree | c62afbc627797cf961d4002207b91738965271a2 /llvm/lib/Analysis/BasicAliasAnalysis.cpp | |
| parent | 028b69009a221e16076be77752514525b321d012 (diff) | |
| download | llvm-83cad6805d144d941bdda99d71a6df2cf113a76d.zip llvm-83cad6805d144d941bdda99d71a6df2cf113a76d.tar.gz llvm-83cad6805d144d941bdda99d71a6df2cf113a76d.tar.bz2 | |
[MLIR][NVVM] Update Float to TF32 conversion Op (#125048)
This change updates the Float to TF32 conversion MLIR Op to include
lowering to the new intrinsics introduced in sm_100 through ptx8.6:
- `nvvm_f2tf32_rn_satfinite`
- `nvvm_f2tf32_rn_relu_satfinite`
- `nvvm_f2tf32_rz_satfinite`
- `nvvm_f2tf32_rz_relu_satfinite`
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
Diffstat (limited to 'llvm/lib/Analysis/BasicAliasAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions