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| author | Min-Yih Hsu <minyihh@uci.edu> | 2021-08-08 15:41:03 -0700 |
|---|---|---|
| committer | Min-Yih Hsu <minyihh@uci.edu> | 2021-08-09 00:07:19 -0700 |
| commit | cf277f0b31df14a0800b6cd30c37b76528cdd520 (patch) | |
| tree | cea000e44f468f53374879b00dfb4add77f1d42e /lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp | |
| parent | 1a18bb9270ce5f6af6633b717058b6b299436203 (diff) | |
| download | llvm-cf277f0b31df14a0800b6cd30c37b76528cdd520.zip llvm-cf277f0b31df14a0800b6cd30c37b76528cdd520.tar.gz llvm-cf277f0b31df14a0800b6cd30c37b76528cdd520.tar.bz2 | |
[M68k][NFC] Coalesce render methods in different asm register op class
And assign RegClass (i.e. operand class for all GPR) as the super class
of ARegClass and DRegClass. Note that this is a NFC change because
actually we already had XRDReg to model either address or data register
operands (as well as test coverage for it). The new super class syntax
added here is just making the relations between three RegClass-es more
explicit.
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp')
0 files changed, 0 insertions, 0 deletions