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author | Mingming Liu <mingmingl@google.com> | 2022-11-02 16:28:49 -0700 |
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committer | Mingming Liu <mingmingl@google.com> | 2022-11-03 12:32:08 -0700 |
commit | f62d8a1a5044df7b8d72033d056375b4ab256012 (patch) | |
tree | 80a472d17f42ca8312afc1254daa360fe57bc8b8 /lldb/test/Shell/ScriptInterpreter/Python | |
parent | 8086b0c8a883ea257519ff48d4445c8ff6a717a0 (diff) | |
download | llvm-f62d8a1a5044df7b8d72033d056375b4ab256012.zip llvm-f62d8a1a5044df7b8d72033d056375b4ab256012.tar.gz llvm-f62d8a1a5044df7b8d72033d056375b4ab256012.tar.bz2 |
[AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection.
Before this patch:
- For `r = or op0, op1`, `tryBitfieldInsertOpFromOr` combines it to BFI when
1) one of the two operands is bit-field-positioning or bit-field-extraction op; and
2) bits from the two operands don't overlap
After this patch:
- Right before OR is combined to BFI, evaluates if ORR with left-shifted operand is better.
A motivating example (https://godbolt.org/z/rnMrzs5vn, which is added as a test case in `test_orr_not_bfi` in `CodeGen/AArch64/bitfield-insert.ll`)
For IR:
```
define i64 @test_orr_not_bfxil(i64 %0) {
%2 = and i64 %0, 127
%3 = lshr i64 %0, 1
%4 = and i64 %3, 16256
%5 = or i64 %4, %2
ret i64 %5
}
```
Before:
```
lsr x8, x0, #1
and x8, x8, #0x3f80
bfxil x8, x0, #0, #7
```
After:
```
ubfx x8, x0, #8, #7
and x9, x0, #0x7f
orr x0, x9, x8, lsl #7
```
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D135102
Diffstat (limited to 'lldb/test/Shell/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions