[AArch64] Add intra-block CSINC optimization to AArch64ConditionOptimizer (#173734)

This patch extends the AArch64ConditionOptimizer pass to handle CSINC
instructions within a single basic block, complementing the existing
cross-block branch optimization.

The optimization finds two CMP+CSINC pairs comparing the same register
with immediates differing by 1, and adjusts one comparison to enable CSE
to eliminate the redundant CMP instruction.

Example transformation:
```
  cmp  w8, #10
  csinc w9, w0, w1, gt     ; w9 = (w8 > 10) ? w0 : w1+1
  cmp  w8, #9              ; Removed by CSE after adjustment
  csinc w10, w0, w1, gt    ; w10 = (w8 > 9) ? w0 : w1+1
```

After optimization:
```
  cmp  w8, #10
  csinc w9, w0, w1, gt     ; w9 = (w8 > 10) ? w0 : w1+1
  csinc w10, w0, w1, ge    ; w10 = (w8 >= 10) ? w0 : w1+1
```

The existing cross-block logic has also been extracted into its own
method.

Any feedback on code quality and better practices is highly welcome.

Co-authored-by: Hussam Alhassan <hsm.link@proton.me>

0 files changed, 0 insertions, 0 deletions