diff options
| author | David Sherwood <david.sherwood@arm.com> | 2022-01-19 11:52:31 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2022-02-02 09:46:02 +0000 |
| commit | 11cf80779654f90faa4e44bda24c7eab049c4a3b (patch) | |
| tree | a612c6ceb54e2a1b910970aa08e6967f41482ec8 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.h | |
| parent | 1c9f15426fb04d6601749da711f41af89869d494 (diff) | |
| download | llvm-11cf80779654f90faa4e44bda24c7eab049c4a3b.zip llvm-11cf80779654f90faa4e44bda24c7eab049c4a3b.tar.gz llvm-11cf80779654f90faa4e44bda24c7eab049c4a3b.tar.bz2 | |
[AArch64][CodeGen] Always use SVE (when enabled) to lower integer divides
This patch adds custom lowering support for ISD::SDIV and ISD::UDIV
when SVE is enabled, regardless of the minimum SVE vector length. We do
this because NEON simply does not have vector integer divide support, so
we want to take advantage of these instructions in SVE.
As part of this patch I've also simplified LowerToPredicatedOp to avoid
re-asking the same question about whether we should be using SVE for
fixed length vectors. Once we've made the decision to call
LowerToPredicatedOp, then we should simply assert we should be using SVE.
I've updated the 128-bit min SVE vector bits tests here:
CodeGen/AArch64/sve-fixed-length-int-div.ll
CodeGen/AArch64/sve-fixed-length-int-rem.ll
Differential Revision: https://reviews.llvm.org/D117871
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.h')
0 files changed, 0 insertions, 0 deletions