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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-09-06 00:19:55 -0400 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-11-29 22:19:33 -0500 |
| commit | 5297cbf04532f61fe18570982f4f2a3095d08c13 (patch) | |
| tree | dbd645bc1c6329c7f233cac3a160e02b71081042 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPythonInterface.h | |
| parent | f1d8345a2ab3c343929212d1c62174cfaa46e71a (diff) | |
| download | llvm-5297cbf04532f61fe18570982f4f2a3095d08c13.zip llvm-5297cbf04532f61fe18570982f4f2a3095d08c13.tar.gz llvm-5297cbf04532f61fe18570982f4f2a3095d08c13.tar.bz2 | |
[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc
Greedy register allocator prefers to move a constrained
live range into a larger allocatable class over spilling
them. This patch defines the necessary superclasses for
vector registers. For subtargets that support copy between
VGPRs and AGPRs, the vector register spills during regalloc
now become just copies.
Reviewed By: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D109301
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPythonInterface.h')
0 files changed, 0 insertions, 0 deletions