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| author | Chenbing.Zheng <Chenbing.Zheng@streamcomputing.com> | 2022-01-24 08:48:39 +0000 |
|---|---|---|
| committer | Ben Shi <ben.shi@streamcomputing.com> | 2022-01-24 08:50:49 +0000 |
| commit | 9aaa74aeeff37b85e29369287ee94773e699b8b7 (patch) | |
| tree | 8f3632e8ee26f13d3af889a4298c8b2c4a3e32dd /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h | |
| parent | 81793bd276afefea0e525307676181478fc614c9 (diff) | |
| download | llvm-9aaa74aeeff37b85e29369287ee94773e699b8b7.zip llvm-9aaa74aeeff37b85e29369287ee94773e699b8b7.tar.gz llvm-9aaa74aeeff37b85e29369287ee94773e699b8b7.tar.bz2 | |
[RISCV] Add patterns of SET[U]LT_VI for STECC forms
This patch optmizes "li a0, 5
vmsgt[u].vx v10, v8, a0"
-> "vmsgt[u].vi v10, v8, 5"
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D118014
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h')
0 files changed, 0 insertions, 0 deletions