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authorAfanasyev Ivan <ivafanas@gmail.com>2025-04-01 17:06:30 +0700
committerGitHub <noreply@github.com>2025-04-01 12:06:30 +0200
commit337bad3921356fba89409e03793f7d2df846c0e9 (patch)
tree039f3737096aecd8a9db1cabf3c1b282426e2d5c /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
parent7f14b2a9eb4792155ed31da7bc16cc58cbb1b0fc (diff)
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[EarlyIfConverter] Fix reg killed twice after early-if-predicator and ifcvt (#133554)
Bug relates to `early-if-predicator` and `early-ifcvt` passes. If virtual register has "killed" flag in both basic blocks to be merged into head, both instructions in head basic block will have "killed" flag for this register. It makes MIR incorrect. Example: ``` bb.0: ; if ... %0:intregs = COPY $r0 J2_jumpf %2, %bb.2, implicit-def dead $pc J2_jump %bb.1, implicit-def dead $pc bb.1: ; if.then ... S4_storeiri_io killed %0, 0, 1 J2_jump %bb.3, implicit-def dead $pc bb.2: ; if.else ... S4_storeiri_io killed %0, 0, 1 J2_jump %bb.3, implicit-def dead $pc ``` After early-if-predicator will become: ``` bb.0: %0:intregs = COPY $r0 S4_storeirif_io %1, killed %0, 0, 1 S4_storeirit_io %1, killed %0, 0, 1 ``` Having `killed` flag set twice in bb.0 for `%0` is an incorrect MIR.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h')
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