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| author | Corbin Robeck <corbin.robeck@amd.com> | 2024-02-16 13:32:59 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-16 13:32:59 -0500 |
| commit | 2d9f3504491156282a3c785a562fcc0ba3c16161 (patch) | |
| tree | ce0fc378be68fe0fda3e89a169f1c3b1e295e561 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h | |
| parent | a4ce870859a2d8b5ce8b92732594089e2a81b4fb (diff) | |
| download | llvm-2d9f3504491156282a3c785a562fcc0ba3c16161.zip llvm-2d9f3504491156282a3c785a562fcc0ba3c16161.tar.gz llvm-2d9f3504491156282a3c785a562fcc0ba3c16161.tar.bz2 | |
[AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit (#81901)
Follow on to #81525 in the series of consolidating bits in TSFlags.
Merge SGPRSpill and VGPRSpill into single Spill bit
Modify isSGPRSpill and isVGPRSpill helper functions to differentiate
VGPR and SGPR spills:
Spill+SALU=SGPR Spill
Spill+VALU=VGPR Spill
The only exception here is SGPR spills to VGPRs which require an
explicit instruction check.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h')
0 files changed, 0 insertions, 0 deletions