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| author | James Y Knight <jyknight@google.com> | 2024-07-25 09:19:22 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-25 09:19:22 -0400 |
| commit | dfeb3991fb489a703f631ab0c34b58f80568038d (patch) | |
| tree | 7117ce620e5bf49aef8810d5651c4aba2b31499e /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.h | |
| parent | 0fedfd83d75415837eb91f56ec24f4b392bf6c57 (diff) | |
| download | llvm-dfeb3991fb489a703f631ab0c34b58f80568038d.zip llvm-dfeb3991fb489a703f631ab0c34b58f80568038d.tar.gz llvm-dfeb3991fb489a703f631ab0c34b58f80568038d.tar.bz2 | |
Remove the `x86_mmx` IR type. (#98505)
It is now translated to `<1 x i64>`, which allows the removal of a bunch
of special casing.
This _incompatibly_ changes the ABI of any LLVM IR function with
`x86_mmx` arguments or returns: instead of passing in mmx registers,
they will now be passed via integer registers. However, the real-world
incompatibility caused by this is expected to be minimal, because Clang
never uses the x86_mmx type -- it lowers `__m64` to either `<1 x i64>`
or `double`, depending on ABI.
This change does _not_ eliminate the SelectionDAG `MVT::x86mmx` type.
That type simply no longer corresponds to an IR type, and is used only
by MMX intrinsics and inline-asm operands.
Because SelectionDAGBuilder only knows how to generate the
operands/results of intrinsics based on the IR type, it thus now
generates the intrinsics with the type MVT::v1i64, instead of
MVT::x86mmx. We need to fix this before the DAG LegalizeTypes, and thus
have the X86 backend fix them up in DAGCombine. (This may be a
short-lived hack, if all the MMX intrinsics can be removed in upcoming
changes.)
Works towards issue #98272.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.h')
0 files changed, 0 insertions, 0 deletions
