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authorShihPo Hung <shihpo.hung@sifive.com>2021-03-08 08:15:06 -0800
committerShihPo Hung <shihpo.hung@sifive.com>2021-03-08 19:30:24 -0800
commit5cdb2e98608bf57c216ee7067e8a12d070c9e2bd (patch)
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[RISCV][MC] Fix nf encoding for vector ld/st whole register
The three bit nf is one less than the number of NFIELDS, so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R. Reviewed By: craig.topper Differential revision: https://reviews.llvm.org/D98185
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