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author | Craig Topper <craig.topper@sifive.com> | 2025-08-04 09:00:41 -0700 |
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committer | GitHub <noreply@github.com> | 2025-08-04 09:00:41 -0700 |
commit | a3a8e1c064d15ce560840279b77e5a421103a58d (patch) | |
tree | abc8d28443db16ef6ae0826a3eae3408ff7e4afc /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
parent | 2fe96439fb81d85ea78a6311b1d9e6ed9b85bcfa (diff) | |
download | llvm-a3a8e1c064d15ce560840279b77e5a421103a58d.zip llvm-a3a8e1c064d15ce560840279b77e5a421103a58d.tar.gz llvm-a3a8e1c064d15ce560840279b77e5a421103a58d.tar.bz2 |
[TargetLowering][RISCV] Use sra for (X & -256) == 256 -> (X >> 8) == 1 if it yields a better icmp constant. (#151762)
If using srl does not produce a legal constant for the RHS of the
final compare, try to use sra instead.
Because the AND constant is negative, the sign bits participate in the
compare. Using an arithmetic shift right duplicates that bit.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions