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| author | Steven Perron <stevenperron@google.com> | 2025-10-09 12:30:58 -0400 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-09 12:30:58 -0400 | 
| commit | ec15cdfb328c504298d0ab14e287448804e6bea5 (patch) | |
| tree | 2a3e443b31883b079e09d408ea8eef920419da77 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 644b068b35b430b279eb3924ac94c6c974588519 (diff) | |
| download | llvm-ec15cdfb328c504298d0ab14e287448804e6bea5.zip llvm-ec15cdfb328c504298d0ab14e287448804e6bea5.tar.gz llvm-ec15cdfb328c504298d0ab14e287448804e6bea5.tar.bz2 | |
[SPIRV][HLSL] Add Sema and CodeGen for implicit typed buffer counters (#162291)
This commit implements the Sema and CodeGen portions of the typed buffer
counter proposal described in the HLSL WG proposal 0023.
This change introduces the necessary Sema and CodeGen logic to handle
implicit counter variables for typed buffers. This includes:
- Extending `HLSLResourceBindingAttr` to store the implicit counter
  binding order ID.
- Introducing the
`__builtin_hlsl_resource_counterhandlefromimplicitbinding`
  builtin.
- Updating `SemaHLSL` to correctly initialize global resource
declarations
  and resource arrays with implicit counter buffers.
- Adding CodeGen support for the new builtin, which generates a
  `llvm.spv.resource.counterhandlefromimplicitbinding` intrinsic for the
SPIR-V target and aliases the main resource handle for the DXIL target.
- Adding and updating tests to verify the new functionality.
Fixes #137032
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
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