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| author | Carl Ritson <carl.ritson@amd.com> | 2023-11-08 11:54:28 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-08 11:54:28 +0900 |
| commit | af6ff98c5338748cd3c38310febb5de31c8e4a37 (patch) | |
| tree | 935857f76f8935fb2291692a0f1f05eb88cb14b5 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 182b7e6ba75055a84544943a06df9964d3a08d81 (diff) | |
| download | llvm-af6ff98c5338748cd3c38310febb5de31c8e4a37.zip llvm-af6ff98c5338748cd3c38310febb5de31c8e4a37.tar.gz llvm-af6ff98c5338748cd3c38310febb5de31c8e4a37.tar.bz2 | |
[AMDGPU] Move WWM register pre-allocation to during regalloc (#70618)
Move SIPreAllocateWWMRegs pass to just before VGPR allocation. This
saves recomputation of the virtual matrix and live reg map, with the
slight regression in O0 that live intervals and slot indexes must be
computed.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
0 files changed, 0 insertions, 0 deletions