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| author | Craig Topper <craig.topper@sifive.com> | 2024-07-27 17:26:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-27 17:26:32 -0700 |
| commit | 9bd97fcf1385efea2dc130ee4fa78665fa6c9205 (patch) | |
| tree | 0a41c96a79a1805e9910fe29fca89c91eecff6e0 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 8f72b0cb08d8b55ef13ed83af8dac2b7ac55208b (diff) | |
| download | llvm-9bd97fcf1385efea2dc130ee4fa78665fa6c9205.zip llvm-9bd97fcf1385efea2dc130ee4fa78665fa6c9205.tar.gz llvm-9bd97fcf1385efea2dc130ee4fa78665fa6c9205.tar.bz2 | |
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
Ventana doesn't have RV32 cores so the instructions aren't really
supported for RV32, but there's nothing specifically 64-bit about them.
My goal here is to fix cannot select errors if XVentanaCondOps is
enabled on RV32. Alternatively, we could quality the lowering code to
also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing
the isel patterns seemed simpler.
Fixes #100855.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
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