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| author | Sanjay Patel <spatel@rotateright.com> | 2021-11-29 16:20:50 -0500 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2021-11-29 17:03:08 -0500 |
| commit | 99f8b795cc03f9bcda7f9cbd9625c2976ae62bd5 (patch) | |
| tree | 45554b42e6231dfa3fc3f40b6b0794234c71d5f1 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 9cf31b8d39d67843eeb314bacf6f78a1c969e1cc (diff) | |
| download | llvm-99f8b795cc03f9bcda7f9cbd9625c2976ae62bd5.zip llvm-99f8b795cc03f9bcda7f9cbd9625c2976ae62bd5.tar.gz llvm-99f8b795cc03f9bcda7f9cbd9625c2976ae62bd5.tar.bz2 | |
[InstCombine] try to fold 'or' into 'mul' operand
or (mul X, Y), X --> mul X, (add Y, 1) (when the multiply has no common bits with X)
We already have this fold if the pattern ends in 'add', but we can miss it if the
'add' becomes 'or' via another no-common-bits transform.
This is part of fixing:
http://llvm.org/PR49055
...but it won't make a difference on that example yet.
https://alive2.llvm.org/ce/z/Vrmoeb
Differential Revision: https://reviews.llvm.org/D114729
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
0 files changed, 0 insertions, 0 deletions