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| author | jacquesguan <Jianjian.Guan@streamcomputing.com> | 2021-07-09 13:15:45 +0800 |
|---|---|---|
| committer | Ben Shi <powerman1st@163.com> | 2021-07-09 13:18:42 +0800 |
| commit | 88326bbce38c53f4782ba3b593b6720438a9569c (patch) | |
| tree | cf7c089fd343d5e7ec344099ee48677235481bc2 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 62cc3cdda64aaaca5bfeba4b131ab6b5f50b4e0c (diff) | |
| download | llvm-88326bbce38c53f4782ba3b593b6720438a9569c.zip llvm-88326bbce38c53f4782ba3b593b6720438a9569c.tar.gz llvm-88326bbce38c53f4782ba3b593b6720438a9569c.tar.bz2 | |
[RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only
with target feature Zvlsseg.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D105626
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
0 files changed, 0 insertions, 0 deletions