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authorDavid Green <david.green@arm.com>2022-02-03 11:05:48 +0000
committerDavid Green <david.green@arm.com>2022-02-03 11:05:48 +0000
commit31373fb88a0a3464013e6ebc5773af27a0603275 (patch)
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parenteaef54f21388350ca72d4dadf33728f70566e531 (diff)
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[AArch64] Reassociate integer extending reductions to pairwise addition.
Given an (integer) vecreduce, we know the order of the inputs does not matter. We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x)))) into UADDV(UADDLP(x)). This can also happen through an extra add, where we transform UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))). This makes sure the same thing happens signed cases too, which requires adding a new SADDLP node. Differential Revision: https://reviews.llvm.org/D118107
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