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| author | Itay Bookstein <itay.bookstein@nextsilicon.com> | 2021-10-08 09:55:55 +0800 |
|---|---|---|
| committer | Wang, Pengfei <pengfei.wang@intel.com> | 2021-10-08 09:57:57 +0800 |
| commit | faa0e2ae7644c332180cfe4e19daf378bc7a46a9 (patch) | |
| tree | b0b2ff8ebaaeb4f277b8ddf942e7c9ab6bda9417 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.cpp | |
| parent | c236883b6ba791881256b31cfdb8a8520a821a67 (diff) | |
| download | llvm-faa0e2ae7644c332180cfe4e19daf378bc7a46a9.zip llvm-faa0e2ae7644c332180cfe4e19daf378bc7a46a9.tar.gz llvm-faa0e2ae7644c332180cfe4e19daf378bc7a46a9.tar.bz2 | |
[SelectionDAG] Fix shift libcall ABI mismatch in shift-amount argument
The shift libcalls have a shift amount parameter of MVT::i32, but
sometimes ExpandIntRes_Shift may be called with a node whose
second operand is a type that is larger than that. This leads to
an ABI mismatch, and for example causes a spurious zeroing of
a register in RV32 for 64-bit shifts. Note that at present regular
shift intstructions already have their shift amount operand adapted
at SelectionDAGBuilder::visitShift time, and funnelled shifts bypass that.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D110508
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.cpp')
0 files changed, 0 insertions, 0 deletions